more choices for your DSP designs

Two recently disclosed digital signal processors (DSPs) from Texas Instruments will expand the world of embedded DSP applications by pushing the performance envelope and shattering price barriers. The TMS320C6202 and TMS320C6211, additions to the world’s most powerful DSP platform, will help designers accel-erate development of products for wireless videoconferencing, wireless e-mail, super-fast Internet access and other applications. The new DSPs are based on the same advanced Very-Long-Instruction-Word (VLIW) central processing unit (CPU) core used in TI’s groundbreaking TMS320C6201, which was introduced last year.

At 2000 MIPS (million instructions per second), the ’C6202 opens doors for more efficient enterprise systems such as wireless base stations, voice-over IP gateways, remote access servers and other multichannel and multifunction commun- ications applications that pack more channels and expanded services into each DSP subsystem. The ’C6211 delivers 1200 MIPS at nearly 2 cents per MIPS. This unprecedented performance value opens possibilities for low-cost, embedded client applications such as asymmetric digital subscriber line (ADSL) modems and advanced imaging.

TMS320C6202: Breakthrough performance

With the capability of executing 2000 MIPS, or 500 million multiply accumulates (MMACS), the ’C6202 propels the DSP architecture 25 percent higher in fixed-point processing performance than the industry-leading ’C6201. A 40 percent reduction in package size means twice the MIPS per square millimeter over the earlier device. The ’C6202 also triples on-chip memory and doubles chip I/O bandwidth for faster data throughput and greater performance in the overall system.

Several key design features contribute to the enhanced performance of the ’C6202. The new DSP integrates three megabits of on-chip random access memory (RAM), tripling the memory of the ’C6201. By increasing clock speed to 250-MHz operation, processing speed increases by 25 percent. The ’C6202 has two 32-bit timers that aid in design flexibility and two multichannel buffered serial ports that interface to T1/E1 and other high-speed communications media. An important new peripheral in the ’C6202 is a 32-bit asynchronous expansion bus that complements the primary, synchronous EMIF bus. The expansion bus provides a nearly glueless interface to PCI bridges and increases the interoperability of the ’C6202 to a wide variety of hosts. In addition, a glueless FIFO interface helps free up the EMIF for real-time, synchronous operation.

TMS320C6211: Affordable performance

Featuring 1200 MIPS of fixed-point performance at $25 in quantities of 25,000, the ’C6211 delivers nearly two cents per MIPS for systems that require advanced signal processing but are sensitive to price. Examples include small office and home office (SOHOs) applications such as DSL client units, high- speed data transmission functions in switches and routers, wireless data clients, imaging, biometrics, remote medical diagnostics, automotive vehicle and drive train control and security systems.

The ’C6211 is the first DSP to employ an innovative 2-level cache memory configuration that provides high performance in a cost-effective solution. Small level-1 program and data caches and a larger, denser level-2 memory block make on-chip memory appear much larger to the DSP’s CPU, enabling faster access with a relatively inexpensive integrated memory. Benchmarks on typical applications show that the ’C6211 achieves more than 80 percent of the performance of a ’C62x device running with all memory on-chip.

Integrated peripheral features also make the ’C6211 well suited for high-performance, cost-sensitive applications. A 32-bit external memory interface (EMIF) supports synchronous access to 1 gigabyte of off-chip memory. Enhanced direct memory access (DMA) supports faster access to mass storage and other input/output (I/O) peripherals. Like the ’C6202, the ’C6211 integrates two 32-bit timers and two multichannel buffered serial ports to facilitate design.

Availability

TI plans to sample the ’C6202 in 1Q99, with volume production scheduled for mid-1999. Samples of the ’C6211 are planned for 2Q99, with volume production scheduled for second half 1999. The ’C6201, the first device in the ’C62x generation, is in volume production today. Samples of the low-power ’C6201B, which dissipates less than 1.9 W, also are available. Additionally, tools supporting the ’C6000 platform are available with an updated version scheduled to ship in October 1998 that will include a simulator specifically designed for the ’C6211.

For more information, order: 'C62x Product Bulletin (SPRT136B). See Related Product Information.