General FAQ

1394 Isolation FAQ

Designer Kits FAQ

TSBKPCI
TSBKPCITST
TSBKGPLYNX
TSBKPRPHRL
TSBKBACKPL

General

Q1: Do any of the TI PHY cores support the following features: Fly by Arbitration, Accelerated ACK, Fairness Optimization, Short Arbitration Reset, and per port disable?

The indicated features are supported in the 41LV0X PHYs.

Q2: Which PHY can be run at 50Mbps? 100Mbps? 200Mbps? 400Mbps?

no cable PHY may run at 50Mbps. However, the TSB14C01A backplane PHY may run at rates of 50 or 100 Mbps. The TSB11LV01 and TSB11C01 can be used at 100Mbps. The TSB21LV03A can be used at rate of 100 or 200 Mbps. The TSB41LV0X family may operate at 100, 200, or 400 Mbps.

Q3: Can a 1394 device be put into “standby” mode to save power?

There is not yet a set "standby" mode for 1394 devices. Several of TI's devices do have a power down mode. These include the TSB11LV01, TSB21LV03A, and TSB41LV0X families. However, when powered down, the PHY will not repeat bus signals to other nodes. Another way to save power is to configure a 1394-1995 node as a repeater. If the link layer does not need to be operational, the PHY may be placed in a repeater mode. In repeater mode the PHY shuts down the PHY-Link interface drivers, disabling all communication with the link including SCLK. But a repeater PHY still "repeats" 1394 cable signals to other nodes on the cable. The node can be configured as a repeater by pulling the PHY Link Power Status (LPS) low. If the PHY LPS pin is connected to the link VDD via a 1K OHM resistor, (for non-isolated mode), removing the supply voltage to the link will pull LPS low on the PHY layer device. If the PHY is still powered it will act as a repeater even though the link is powered down. As a repeater, the node can not originate or receive packets, since the PHY-link interface and the link will not be operational. However, it will repeat packets to other nodes on the bus. It should be noted that most link layers do not function if SCLK is not provided. If LPS is not asserted, SCLK is not provided to the link. Therefore LPS should not be de-asserted if the link layer must remain active.

Q4: Are resistors or capacitors needed for unused PHY ports?

If the "unused" ports will NEVER be used then it is OK to leave the associated TPBIAS and TPA+/TPA- pins unconnected. However, the TPB+/TPB- pins should NOT be left unconnected (floating). These pins should be tied together and connected to the Link ground plane via a ~5K OHM resistor. The value of the resistor is not that important. In fact it may be 0OHM. It just has to be low enough to insure that the pins are pulled low at all times. If the port may be used in the future it is recommended that you include the entire termination network.

Q5: How should AVDD, DVDD, PLLVDD, AGND, DGND, and PLLGND pins be separated to reduce noise?

Normally there is not a noise problem, and all the VDD pins may be tied together on one power plane. All the GND pins may be tied together to a single GND plane. The VDD_5V pin must be tied to a 5 volt supply only if the part will be exposed to 5 volt signaling levels. If the only signals driven are from 3.3 volt devices, VDD_5V may be connected to digital 3.3V VDD. To prevent noise on the DGND and DVDD planes getting on the AVDD, AGND, PLLVDD, PLLGND pins and causing problems, decoupling capacitors can be used on each individual power pin on its local plane. High frequency response capacitors (typically ceramic) should be used and placed as close as possible to the supply pins. The PLLVDD and PLLGND pins are more sensitive to noise than AVDD and AGND and should have the most care taken in placement of capacitors. If the VDD_5V is connected to a 5 Volt plane it should have its own decoupling capacitor. What should NOT be done is to short all these pins together with a few top layer traces and have a common decoupling capacitor for several different power inputs (AVDD & DVDD & PLLVDD). As a minimum requirement, the board should be designed so that each power pin should be connected to the power plane with as short a trace as possible. Each power pin should have it's own decoupling capacitor, or at least only share a decoupler between common power pins. If the user desires the DVDD, AVDD, and PLLVDD planes may be separated and connected using very low DC impedance filter networks with the proper decoupling capacitors for each plane.

Q6: What is “Power Class?”

The power class is used to define if a 1394 node is a cable power user, cable power provider, or both, and how much power it uses/provides. The definitions for the eight power classes are given in the IEEE 1394-1995 standard section 4.3.4.1 Table 4-29. The setting used will depend on whether you will use power from the 1394 cable, if you will power your PHY and Link from local power, or if you will be providing power from your node onto the 1394 bus.

Q7: What is the crystal spec for the TI PHYs?

TI PHYs may use an external 24.576MHz crystal connected between the XI and XO pins on the PHY to provide the PHY clock. The following are some typical specifications for the crystals used with the Physical Layers from TI. The clock resulting from the input from the crystal must be within the tolerance of +/-100 parts per million for the PHYs to function correctly. This is required by the 1394 standard. This frequency tolerance for the PHY clocks on each node must be maintained over the variation introduced over production runs of boards and environment the machines operate in. Every board must have an SCLK (clock generated by the PHY) within +/-100 ppm of 49.152MHz to be compliant to the 1394 standard. If adjacent nodes are more than 200ppm away from one another then long packets sent across the 1394 bus may be corrupted, with the final bits of the packet being lost. TI PHYs are designed with a maximum of margin, but the limits imposed by 1394 must still be adhered to. 1.Crystal Mode of operation: Fundamental 2.Frequency Tolerance @ 25 Degrees C: Total variation specification for the complete circuit is 100ppm. The crystal is specified at less than 100ppm. We currently specify ours at +/-30ppm. 3.Frequency stability (over temp): Total variation specification for the complete circuit is 100ppm. The crystal is specified at less than 100ppm. We currently specify ours at +/-30ppm. Note: The total variation must be kept below 100ppm with some allowance for variation introduced by variations in board builds and device tolerances. So the sum of the frequency tolerance and the frequency stability must be less than 100ppm. This can be traded off between the two, for example the frequency tolerance may be specified at 50ppm and the temperature may be specified at 30ppm to give a total of 80ppm possible variation just due to the crystal. 4.Load capacitance: (Parallel (pF)) We have used parallel mode crystal circuits since they are more stable and precise. Load capacitance will be a function of your board layout and circuit. The total load capacitance (CL) will affect the frequency the crystal oscillates at. You will need to consult with your crystal vendor and will have to iterate your design to get an SCLK supplied by the PHY to less than 100ppm from 49.152MHz . We recommend that a maximum of +/-5% tolerance load capacitors be used. For our OHCI + 41LV03 Evaluation Module (EVM) with a crystal specified for 20pF loading we found a value of 33pF for each load capacitor (C9 = C10 below) to be appropriate with the layout used for the board. The load specified for the crystal includes the load capacitors (C9, C10), the loading of the PHY pins (Cphy), and the loading of the board itself (Cbd). To summarize: CL =[ (C9*C10) / (C9+C10)] + Cphy + Cbd. Representative values for Cphy are ~1pF and for Cbd are about 0.8pF per centimeter of board etch, a "typical" board can have from 3pF to 6pF or more. The capacitance of load capacitors C9 and C10 combine as capacitors in series. Note: The layout of the crystal portion of the PHY circuit is important for getting the correct frequency from the crystal, minimizing the noise introduced into the PHY Phase Lock Loop, and minimizing any emissions from the circuit. The crystal and the two load capacitors should be considered a unit during layout. The crystal and the load capacitors should be placed as close as possible to one another while minimizing the loop area created by the combination of the three components. Varying the size of the capacitors may help in this. Minimizing the loop area minimizes the effect of the resonant current (Is) that flows in this resonant circuit. This layout unit (crystal and load capacitors) should then be placed as close as possible to the PHY XI and XO pins to minimize etch lengths. We strongly recommend that part of the verification process for your design be to measure the frequency of the SCLK put out by the PHY. This should be done with a frequency counter with an accuracy of 6 digits or better. If the SCLK is more than the crystal tolerance away from 49.152 MHz, the load capacitance of the crystal may be varied to see if this brings it into line. If the frequency is too high add more load capacitance, if the frequency is too low decrease load capacitance. Typically changes should be done to both load capacitors (C9 and C10 above) at the same time to the same value. It is suggested that you talk with the crystal vendors for a more detailed understanding of what is required. In order for a 1394 bus to operate correctly each SCLK on each node on the bus must be within 200 ppm of the adjacent SCLK on the bus. The 1394 standard requires this by specifying a center frequency of 49.152MHz and a +/-100ppm tolerance around 49.152 MHz. We have used crystals from the three vendors listed: Fox Electronics 813-693-0099 813-693-1554 FAX SaRonix 415-856-6900 Comclok, Inc. 714-991-1580 800-333-9825 (In CA)

Q8: Do any PHYs support a power-down mode?

The TSB11LV01, TSB21LV03A, and TSB41LV0x each have a CMOS input, PD (Power Down) pin which, when asserted high, turns off all internal circuitry except the CNA (Cable Not Active) monitor. The CNA pin along with other logic can be used with the PD pin to shut down the PHY circuitry when no cables are attached. It should be noted that most link layers do not function if SCLK is not provided. If PD is asserted, SCLK is not provided to the link. Therefore PD should not be asserted if the link layer must remain active.

TSB21LV03A

Q1: How is the TSB21LV03A operated at 100Mbps?

To use the TSB21LV03A 200Mbps PHY at 100Mbps the appropriate signal from the link chip needs to be sent to the PHY on the "LREQ" pin. The Link Bus Request LR [4:5] bits indicate the speed. “00” signals 100Mbps and “01” signals 200Mbps.

Q2: What is the TSB21LV03A pin 27 resistor function?

Pin 27 on the TSB21LV03A PHY is defined as input/output C/LKON. As an input, this terminal indicates whether the node is bus manager capable. If software supports this, it can be signaled via a gpio output (such as gpio_data0) from the link. A pull-down or pull-up resistor is required on this terminal to pull the signal to a known DC state. As an output, the pin functions as a Link On (LKON) output when the PHY receives a LKON PHY packet. If the PHY receives a LKON packet while its LPS is low, then the PHY drives a ~6MHz square wave out the LKON pin. The signal is terminated when LPS goes high signaling that the link has been powered on.

Q3: Is the crystal oscillator input X1 a CMOS input?

XI is a CMOS input to the TSB21LV03A PHY when using an external oscillator.

Q4: The TSB21LV03 exhibits spurious bus resets at 200 Mbps for more than 5 hops. (21LV03 Errata Item #12) Is this true for 100Mbps?

The TSB21LV03 does not exhibit the spurious bus reset problem at 100Mbps. The TSB21LV03A ("A" revision) part does not exhibit this behavior and should be used in the future to allow 200Mbps operation with more hops.

Q5: What is the difference between R0 and R1? Is the 6.3kOHM resistor necessary?

R0 is a local GND pin while R1 is a reference voltage. The resistance between R0 and R1 must be within 6269 Ohms and 6331 Ohms over the operational temperature range of the system to stay in spec with the IEEE 1394-1995 standard. The resistor between R0 and R1 sets the currents (and therefore the voltages) driven on the 1394 cable.

TSB14C01A

Q1: Can a TSB12LV31 be connected to a TSB14C01A?

Yes. Note, however, that the TSB12LV31 has limited size asynchronous FIFOs. It is optimized to act as an isochronous source or sink. A TSB12LV31 can connect to a TSB14C01A by using the 5V tolerant bias terminals on the TSB12LV31 (pins 12,37,62,87). Pull-up resistors on the CTL and DATA lines should not be required. The VIH for the TSB14C01A is 2V while the VOH for the TSB12LV31 is (Vcc - .6) or 2.4V at a minimum Vcc of 3V for the Link. The 2.4V is rated at 12ma.

Driver/Receiver Voltage Levels for TSB14C01A and TSB12LV31

	TSB14C01A	TSB12LV31
Receiver (TTL)	VIH(min)=2.0V VIL(max)=0.8V	VIH(min)=2.0V VIL(max)=0.8V
Driver (TTL)	VOH(min)=4.45V VOL(max)=0.5V	VOH(min)=2.4V VOL(max)=0.4V

Q2: What is the recommended backplane driver part?

This is mostly up to the designer and what backplane technology is being run and how fast it is being run. Please see the "transceiver selection" section of the TSB14C01A data sheet.

TSB11C01

Q1: Are the TSB11C01 link interface pins TTL compatible?

No, the TSB11C01 link interface pins are NOT TTL compatible. As a result, the TSB11C01 should not be directly connected to a low voltage (3.3 V nominal) link layer controller. The TSB11C01 does not have TTL thresholds. Instead it has thresholds centered to accommodate IEEE 1394-1995 Annex J suggested isolation. Interoperability can not be guaranteed with the combination of the TSB11C01 PHY and a low voltage link device. The TSB21LV03A, TSB11LV01, or the TSB41LV0X (or other low voltage PHYs) should be used in applications needing a low voltage link layer. Voltage Levels for 11C01 receivers/drivers: Receivers (CMOS) VIH (min) = 3.5V VIL (max) = 1.0V Drivers (CMOS) VOH (min) = 3.7V VOL (max) = 0.5V