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In This Issue

   DSP Solutions
The latest word in Wireless
The power of 1V
Finally! Chip technology matches
  designer imagination

   Memory
New 64-Mbit SDRAMs
   now sampling

Hitachi, Mitsubishi and TI
  to develop 1-GB DRAMs

   Other Stories
Make your PCI bus
  perform 4x faster

TI-Japan, Matsushita develop
  1394 IC for digital video

   Product Update
Power+ FET pre-drivers
Test-drive the TMS320C54x

Trade Shows

Quicker Recall

New 64-Mbit SDRAMs now sampling

A new family of low-power, 64-megabit synchronous DRAM (SDRAM) memories are now available in sample quantities from TI.

Designated the TMS664xxx family, the 3.3-V devices allow designers to improve system performance by increasing memory bandwidth, while keeping the system's physical size and power requirements to a minimum. Applications that can benefit include servers, work-stations and portable computers.

TMS664xxx features
  • Up to 100 MHz
  • Individual bank or interleaved access
  • Two refresh modes
  • Programmable burst read lengths and latencies
  • LVTTL interface
Device types available

Device

Configuration

TMS664414

4M x 4 x 4 banks

TMS664814

2M x 8 x 4 banks

TMS664164

1M x 16 x 4 banks

"As evidenced by Microsoft's PC'97 initiative, the trend in the industry is toward systems that require more memory and, at the same time, very high-speed memory," said Bob Harrison, TI's MOS memory marketing manager for the Americas. "Our TMS664xxx family of SDRAMs delivers on both counts. These devices can respond very quickly to data requests from the system's microprocessor, PCI bus, Advanced Graphics Port, Universal Serial Bus and 1394 peripheral bus."

 Fabricated with 0.3-micron CMOS technology, the TMS664xx family currently supports clock rates of 100, 83 and 66 MHz. Plans for second-generation devices call for speeds of up to 143 MHz.

 Designed for flexibility, the TMS664xxx devices are organized in four banks, each of which can be accessed individually or by interleaving. The memories are capable of either a 4K automatic refresh mode or a low-power self-refresh mode. The burst length of data reads can be programmed to one, two, four, eight or a full page of addresses; and read latencies can be set at two or three cycles. The devices also feature a high-speed, low-noise Low-Voltage TTL (LVTTL) interface.

Samples of TMS664xxx memories are available in JEDEC-standard 400-mil, 54-pin thin small outline (TSOP) packages and 168-pin dual in-line memory modules (DIMMs). Volume production is scheduled for 3Q97.

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