Application Report: Performance analysis of line-echo-cancellation implemention using TMS320C6201

The TMS320C6201 currently delivers up to 1600 MIPS at 200 MHz and has a roadmap to nearly double this performance by the year 2000. This high-performance solution features dual data paths, eight functional units including two multipliers and six arithmetic logic units (ALUs) allowing execution of eight, 32-bit instructions in parallel, and five DMA channels with automatic address generation features. This allows the TMS320C6201 to deliver up to 10 times the performance of previous DSPs, providing a solution well suited for multichannel telephony applications such as line echo cancellation.

The table below highlights the key performance attributes of the ’C6201 performing echo cancellation.

32-ms
Echo Tail 48-ms
Echo Tail 64-ms
Echo Tail

Data memory requirements per channel 1084 bytes 1852 bytes 2108 bytes

Cycles required per channel (LMS) 388 cycles 532 cycles 676 cycles

Cycles required per channel (Leaky LMS) 484 cycles 676 cycles 868 cycles

Channels per 200-MHz ’C6201 (LMS) 59 34 30

Channels per 200-MHz ’C6201 (Leaky LMS) 51 34 28

This analysis shows that ’C6201 offers a high-performance and cost-effective solution to multichannel line echo cancellation.

Compared to other dedicated processors for echo cancellation, the ’C6201 provides much more flexibility in algorithm design so that users can tailor the implementation to meet the special requirements for their application.