The new ADSL chipset is built upon a flexible architecture specifically designed to keep pace with the still evolving needs and standards of the ADSL market. TI's ADSL architecture delivers unparalleled benefits to equipment manufacturers, service providers and consumers by incorporating the following key principles:
- Performance.
Leveraging Amati Communications' previous four generations of ADSL modem experience and raw processing power of the TMS320C6x technology, the chipset will offer the industry's highest throughput, longest reach and most robust ADSL modem performance.
- Scalability.
The ADSL transceiver will have the power to handle two full-rate lines and as the technology advances, the transceiver will handle additional ADSL lines. This multi-line architecture enables equipment vendors to develop high-density DSLAM devices for central office and point-of-presence (POP) deployment by reducing board space, power requirements and per-port costs.
- Programmability.
TI's ADSL chipset will offer a programmable solution for both infrastructure and remote client/PC applications. This programmability enables quick and easy code fixes, code updates and feature additions simply by downloading new software to the chip. TI will also take advantage of the programmable architecture to develop future code loads supporting applications such as G.lite, a consumer-based splitterless modem standard.
- Extensibility.
The architecture of the chipset was specifically designed to enable future derivatives to be brought to market quickly. By optimizing portions of the current chipset architecture and adding new functions such as Asynchronous Transfer Mode (ATM), Protocol Control Information (PCI), Universal Serial Bus (USB) or Ethernet interfaces, Texas Instruments will be able to quickly spin tailored versions of the chipset to better meet specific market segment requirements. In addition, the architecture will eventually enable equipment vendors to support different networking technologies, routing stacks, encryption, network management and data compression on the ADSL chipset.
