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Inside
Showcase (Volume 27) is available in HTML and
PDF format. - 179KB
PowerFLEX™, a low-cost alternative to TO-220
High performance PLL clock drivers
Digital control loop for 3-phase brushless dc motor
Cost-effective gigabit ethernet transceiver
SN75LVDM976, industry's first discrete dual mode LVDS SCSI transceiver
TRF2050, a 1.2 GHz fractional-N/integrator-N syntheszier
New external memory interface provides 8 hour speech duration
Sine-on, TI's information service for analog engineers
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Portfolio of high performance PLL
clock drivers
Product Features
- Zero delay PLL buffers
- Low 3.3-V supply
- High operating frequency up to 125 MHz
- Integrated loop filter
- Output enable for each output bank
- Characterized for operation from 0°C to 70°C
Texas Instruments’ new family of high performance phase-lock-loop (PLL) clock drivers features the CDC509, CDC516, CDC2509, CDC2510, and CDC2516. Each device is designed to precisely align, both in frequency and in phase, the feedback output (FBOUT) to the clock (CLK) input signal making the devices suitable for high end synchronous DRAM applications.
Each bank of outputs provides low-skew, low-jitter copies of the input clock. The output signal duty cycle is adjusted to 50%, independent of the duty cycle at the input clock. Each bank of outputs can be enabled or disabled separately via the control (G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK. When the G inputs are low, the outputs are disabled to the logic-low state.
Compared to other PLL devices, the family features integrated loop filter alleviating the need for external components reducing board space and cost. External feedback input (FBIN) enable each device to be used as a zero delay buffer. With their low voltage (3.3 V) and low power capabilities, these devices are optimized to reduce switching noise. Integrated series damping resistors make the 2000-series suitable for driving point-to-point loads. The 500-series are designed to drive multiple memory loads.
With its low cost, high performance, and zero delays, the family is designed to target high speed applications such as: SDRAM DIMMs (dual-inline memory modules) for PCs, servers, and workstations, and general purpose clocking.
The family of PLL clock drivers is available in plastic thin shrink small outline surface-mount packaging (TSSOP) for reduced printed board space requirement.
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Device | Application | Banks/Outputs | Pins/Package |
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CDC509 | 128M SDRAM DIMM | 1/5 & 1/4 | 24/TSSOP |
| CDC516 | 256M SDRAM DIMM | 4/4 | 48/TSSOP |
| CDC2509 | 128M SDRAM DIMM | 1/5 & 1/4 | 24/TSSOP |
| CDC2510 | 256M SDRAM DIMM | 1/10 | 24/TSSOP |
| CDC2516 | 256M SDRAM DIMM | 4/4 | 48/TSSOP |
Vol 27 May, 1998
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