TMS320C6x DSPs: Performance and cost-efficiency

At the heart of the 'C6x design is VelociTI™, advanced Very Long Instruction Word (VLIW) architecture that provides a simple, cost-effective way of controlling the parallelism inherent in DSP algorithms. Figure 3 illustrates the basis of the VLIW architecture. VelociTI increases the parallel execution of instructions by fetching and executing up to eight 32-bit instructions in each cycle, reducing code size, program fetches and power consumption. All instructions are conditional, minimizing branching for higher sustained performance. An advanced C compiler generates code that executes on highly-independent functional units, with triple the efficiency of existing fixed-point DSP compilers. The architecture is also scalable to support architectural enhancements in future product generations.

VLIW architecture

Figure 4. The TMS320C6x features the advanced Very Instruction Word VelociTI architecture that provides simple, cost-effective control of the parallelism inherent in DSP operations.

In the past, DSP developers have had to maximize software performance through the time-consuming task of hand-crafting assembly code for the device. The efficiency of the 'C6x software tools allows software engineers to code in high-level C code, without concern for the mechanics of the underlying processor. The shift in programming from assembly to C cuts development time in half and opens up product development to a wide pool of C applications programmers who can immediately take advantage of the power of the 'C6x -- even if they have no previous experience with DSPs. Programming in C allows developers to focus on their application-level core competencies, decreasing time-to-market and making DSP application software easier to develop and use.

For key applications that can still benefit from fine-tuning in assembly code, TI has developed an Assembly Optimizer for 'C6x-generation processors. The Optimizer brings to assembly programmers the same kinds of tools that were previously found only in high-level language programming. Programmers can transparently target the 'C6x VLIW architecture by automatically scheduling linear assembly code to run in parallel. By allocating processor resources such as registers and memory address locations, the Assembly Optimizer shields programmers from having to understand the minutiae of the processor architecture. Tools with these features are unprecedented at the assembly level. Figure 4 shows how the 'C6x tool set works together to support product development.

TMS320C6x development tools

Figure 5. A world-class set of development tools harnesses the power of the 'C6x, shifting the paradigm of DSP development from hardware to software.

The new design standard enabled by TI's 'C6x DSP processor generation gives product developers the same performance level of custom application-specific ICs (ASICs), but with the flexibility of a programmable processor. The 'C6x eliminates the need for the time-consuming, expensive design of an ASIC, allowing designers to focus on developing their products in software.

Furthermore, with an ASIC, months may be required to implement even minor design alterations, such as those accommodating protocol standards that have been updated. The same changes can be implemented in minutes with software on the 'C6x, but without compromising system performance.

The first 'C6x products are designed using 0.25-yum CMOS technology, with a roadmap in late 1997 to 0.18-um CMOS based on TI's 125-million-transistor TImeline™ technology. Because these processes are thrifty in power consumption, 'C6x-based systems will run cooler and be less expensive to operate.

The industry's highest-performance DSP

TI's initial offering in the 'C6x generation is the TMS320C6201, a fixed-point device operating at 200 MHz. Featuring eight instructions per cycle, the 'C6201 can process up to 1600 MIPS -- more than ten times the performance of previous DSPs. Among the operations used heavily in communications, multiply-accumulate operations (MACs) can be accomplished 400 million times per second, and a 1024-point complex Fast-Fourier Transform (FFT) requires only 70 us. On-chip peripherals such as RAM, dual timers and serial ports further tailor the 'C6201 for base station systems. Figure 5 shows the advanced internal architecture of the 'C6201.

Using a 'C6201, an OEM can implement a base station with 30 extended full-rate (EFR) GSM channels at a mere $3 per channel, compared with five channels at $7 per channel with competing solutions. The 'C6201 solution not only cuts system cost by more than half, it also lowers the chip count and dramatically reduces system space. Now a 128-channel base station can be built using only four 'C6201 DSPs, as opposed to 24 DSPs previously.

TMS320C6201 block diagram

Figure 6. The elegant simplicity of the 'C6201 architecture supports performance of 1600 MIPS at 200 MHz -- 10 times the performance of previous DSP.

TI created the 'C6x DSP core to be used with its customizable DSP (cDSP™) design approach, allowing the company to introduce new products quickly in order to meet specific market demands. Figure 6 shows the roadmap for further growth of the 'C6x DSP generation. The cDSP approach allows the company to tailor on-chip RAM, ROM and Flash memories to meet the requirements of individual applications, and also to introduce important functions such as host bus interfaces and additional serial ports. TI has the logic and mixed-signal functions required to support a wide variety of high-performance DSP applications, as well as the ASIC design and process technologies needed to integrate these functions successfully. In addition, TI will offer software modules supporting the major international wireless standards to help its customers simplify their development and speed time-to-market.

Wireless OEM customers also benefit from the vast system-level expertise TI has gained from base station and handset designs worldwide. With an international design, support and manufacturing infrastructure, TI offers its customers the support they need in their own global businesses. TI's manufacturing strength assures its customers of secure supplies and fast volume ramp-up. Finally, the company's Wireless Business Unit leverages all of TI's many technological strengths for the benefit of its wireless customers.

The key to a wireless future

As an essential element of wireless communications, base stations must meet the demands of consumers for greater capacity, better voice quality, and more advanced features such as faster data communications -- all at a lower cost. At the same time, base stations are evolving from enormous macrostations with vast transmitting power to minute, special-purpose picostations with smaller transmitting power but higher processing loads. TI's new TMS320C6x generation of DSPs is designed to help OEMs provide base station products that can meet the evolving needs of the wireless marketplace. Just as earlier generations of TI DSPs have served to increase the performance and decrease the cost of wireless telephones, 'C6x DSPs will be a key enabler of wireless base stations into the next century.

TMS320C6x product roadmap

Figure 7. Upcoming 'C6x products will leverage TI's leadership in customizable DSP (cDSP) development to offer even higher level of integration and performance.