68HC12 CPU and Peripheral Overview

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68HC12 Central Processor Unit (CPU12)
At the core of the 68HC12 is CPU12, a high-speed 16-bit evolution of the 68HC11 architecture that is designed to maintain complete source-code compatibility with the 68HC11 core. The 68HC12 fully supports all internal registers, instructions, addressing modes, and operating modes of the 68HC11.

Additional features and benefits include:

  • Up to 8 MHz bus speed at 5 V
  • Up to 5 MHz bus speed at 3 V
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  • 64 new instructions, 20-bit Arithmetic Logic Unit (ALU), instruction queue, and 7 new indexed addressing modes
  • 16-bit data paths
  • 64 Kbytes of linear and paged memory addressing capability, enabling access to more than 4 Mbytes of program space and 1 Mbyte of data space
  • Call and Return from Call (RTC) instructions for efficient paged addressing
  • High-level language (HLL) optimization
  • Fast math capabilities (16 x 16 MUL, 32 ÷ 16 DIV, EMACS)
  • Fuzzy logic instructions for simplified programming, reduced code size, and faster code execution
  • Low-power wait and stop modes
    •  Flexible Modular Design
    A standard bus interface-the Lite Module Bus (LMB) designed for low power- is used to connect the CPU12 to specialized peripheral modules. The LMB is similar to the Intermodule Bus (IMB) found on the 68HC16, 68300, and MPC500 Families, allowing Motorola to leverage existing, proven peripheral modules to develop new 68HC12 derivatives.

    Low Power, Low Voltage, Low Noise
    The 68HC12 runs at up to 8 MHz and was designed for extended voltage range operation as well as low-power consumption. Devices operate from 3.0 V to 5.5 V.

    Low-power operation is achieved through:

  • Stop and wait modes
  • Ability to shut down peripherals
  • Phase-Locked Loop (PLL) system clock on some derivatives
  • Fewer bus interface and address lines
  • Signals propagated on the bus only as needed
  • Programmable output drivers on most I/O ports reduce noise and power consumption
    •  Background Debug Mode (BDM)
    The 68HC12 offers the Motorola's Background Debug(tm) in-circuit debug capability used to decrease time-to-market. This enhanced, patented version of the Background Debug Mode found on our 68HC16 and 68300 microcontrollers replaces conventional debug modes. It allows non-intrusive, real-time read/write capability to the memory and registers for faster code debugging. It also allows FLASH re-programmability in the field for diagnostics and upgrades of customer end products. Background Debug Mode features/benefits include:
  • Single-wire communication protocol
  • Simple commands used to debug while in-circuit
  • In-circuit programming of FLASH EEPROM and byte-erasable EEPROM
    •  FLASH EEPROM Memory
    Some derivatives of the 68HC12 Family feature on-chip non-volatile FLASH EEPROM memory that is bulk erasable and supports byte or aligned word operations. In addition, fast termination is assured with single-cycle access speed, and an optional 1 to 2 Kbytes of protected boot block is available. This innovative, 16-bit wide memory subsystem offers many benefits, including:
  • In-circuit programming through Background Debug Mode
  • Field re-programmability
  • Fast programming and erase times
  • Faster time to market
  • Production units that can be customized at end of process
    •  Byte Erasable EEPROM Memory
    The 68HC12 Family also features on-chip byte-erasable EEPROM for enhanced programming flexibility with no separate supply voltage required. This integrated non-volatile memory solution enables:
  • Storage of calibration information
  • Self-adjusting or self-adapting systems
  • Data logging for historical or secure data
  • Jump tables and code patches
    •  High Performance Timer
    The 68HC12 timer provides flexibility, performance, and ease of use. The system is based on a free-running, 16-bit counter with a programmable prescaler, overflow interrupt, and separate function interrupts.

    Additional M68HC12 timer features include:

  • Multiple timer channels
  • Each channel configurable for either input capture or output compare functions
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  • Real-time periodic interrupts
  • Computer Operating Properly (COP) watchdog protection against software failures
  • Pulse accumulator for external event counting or gated time accumulation
  • An optional PWM offering up to four channels and up to 16-bit PWM outputs
  • Optional event counter system for advanced timing operations
    •  Analog-to-Digital Converter (ADC)
    The ADC periodically samples external analog signals and produces corresponding digital values. Typical applications are measuring analog inputs like battery voltage, temperature, pressure, and fluid levels.
  • Linear successive approximation
  • 8-bit or 10-bit resolution
  • Single or continuous conversion modes
  • Multiple result registers
  • Selectable ADC clock
  • Analog multiplexer allows variable number of channels with a single ADC
    •  Pulse-Width Modulation
    The 68HC12 Family offers a selection of Pulse-Width Modulation (PWM) options to support a variety of applications. Up to four PWM channels can be selected to create continuous waveforms with programmable rates and software selectable duty cycles from 0 to 100%.

    Serial Peripheral Interface (SPI)
    The SPI communicates synchronously over short distances (usually on a single PCB) at high speed. The SPI allows the microcontroller to communicate with peripheral devices such as a simple shift register, a serial EEPROM, or a complete LCD or ADC subsystem.

  • Full-duplex, three-wire synchronous transfers
  • Master or slave operation
  • Maximum master bit frequency is bus frequency divided by 2
  • Maximum bit rate of 4 MHz for an 8 MHz system clock
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  • Maximum slave bit frequency is bus frequency
  • Maximum bit rate of 8 MHz for an 8 MHz system clock
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  • Four programmable master bit rates
  • Programmable clock polarity and phase
  • End of transmission interrupt flag
    •  Serial Communications Interface (SCI)
    The SCI is a serial UART-type asynchronous communications system. The SCI can be used for communications between the microcontroller and a terminal, a computer, or in network of microcontrollers. A typical SCI application is long-distance communications (RS-232).
  • Standard mark/space non-return-to-zero format
  • Full-duplex operation
  • Double buffering of both transmitter and receiver
  • Separately enabled transmitter and receiver
  • Programmable 8-bit or 9-bit character length
  • Advanced error detection at 1/16 of a bit time
  • Baud rate generator with programmable baud rates
  • Idle line and address mark wakeup methods
  • Receiver framing error detection
  • Break send capability
  • Optional hardware parity checking and generation
  • Separate transmitter, receiver, and error interrupt vectors
    •  Motorola Scalable CAN Module (MSCAN)
    The Controller Area Network, or CAN, protocol is a serial communication protocol originally developed by Robert Bosch GmbH for use in serial communication networks in vehicles. Several major auto manufacturers are either currently using CAN networks in their vehicles or are developing them for future vehicles. In addition, CAN is becoming very popular for use in factory-floor automation-type industrial networks.

    The Motorola Scalable CAN module (MSCAN) is an advanced communications controller implementing the CAN protocol with these features:

  • Implementation of CAN version 2 parts A and B
  • Standard (11-bit) and extended (29-bit) data frames
  • 0 to 8 bytes data length
  • Programmable bit rate up to 1 Mbps
  • Support for remote frames
  • Double buffered receive
  • Triple buffered transmit with internal prioritization using a "local priority" concept
  • Flexible maskable identifier filter supports alternatively two full size extended identifier filter, four 16-bit filters, or eight 8-bit filters
  • Programmable wakeup functionality with integrated low-pass filter
  • Programmable loopback mode supports self-test
  • Separate signaling and interrupt capabilities for all CAN receiver and transmitter error states (warning, error passive, bus-off)
  • Programmable MSCAN clock source (either the CPU bus clock or the crystal oscillator output)

    • Low-power sleep mode     SAE J1850 Byte Data Link Control Module (BDLC-D)
    The BDLC-D is an advanced serial communication multiplex bus controller operating according to the SAE J1850 Class B protocol. Typical applications of the BDLC module are in automobiles where multiple BDLC MCUs can communicate over a single or dual wire bus, eliminating the weight and bulk of wire harnesses and adding diagnostic capability.
  • SAE J1850 compatible
  • 10.4 kbps variable pulse width (VPW) bit format
  • Digital noise filter
  • Collision detection
  • Hardware cyclical redundancy check (CRC) generation and checking
  • Two power-saving modes with automatic wakeup on network activity
  • Polling and CPU interrupts available
  • Receive and transmit block mode supported
  • Supports 4x receive mode (41.6 kbps)
  • Digital loopback mode
  • Analog loopback mode

    • Supports in-frame response (IFR) types 0, 1, 2, and 3


    68HC12 Product Overview

    68HC12 A Family:
    The 68HC12 A Family features expanded bus MCUs that operate from 3.0 - 5.5V.  Other features of this family include 4Kbytes EEPROM,  up to 5 MByte external addressing capability, PLL, and dual SCI modules.

    68HC12 B Family:
    The 68HC12 B Family is the world's first 16-bit MCU to include both FLASH EEPROM and byte-erasable EEPROM integrated on-chip.  All devices in this family incorporate an advanced serial communication multiplex bus controller operating with either the Byte Data Link Control Module (68HC912B32 and 68HC12BE32) or the Controller Area Network Module (68HC912BC32).

    68HC12 D Family:
    The 68HC12 D Family is one of our most highly integrated 16-bit MCUs.  All devices in this family incorporate dual SCI modules, a Controller Area Network Module for advanced serial communication, dual 10-bit ADC modules, large program and data memory arrays using both FLASH and byte-erasable EEPROM, PLL, and keyboard interupts.

    68HC12 Development Tools Overview

    Motorola and several independent development tool suppliers offer both hardware and software development tools for the 68HC12 Family. Motorola offers the HC12 Development Kits which include the device-specific Evaluation Board, the Serial Debug Interface (SDI), and the MCUez(tm) development toolset.

    HC12 Evaluation Boards
    The device-specific Evaluation Boards (EVB) are economical tools for designing and debugging code for, and evaluating the operation of, the 68HC12 microcontrollers. By providing the essential MCU timing and I/O circuitry, the EVBs simplify user evaluation of prototype hardware and software. The EVBs feature a prototype area, which allows custom interfacing with the microcontroller's I/O and bus lines. Some EVBs can also accommodate various types and configurations of external memory to suit a particular application's requirements.

    Serial Debug Interface (SDI)
    Motorola's SDI is a serial in-circuit debugger, that uses the Background Debug(tm) Mode on the M68HC12 microcontroller, allowing quick verification and updating of embedded software. When used with compatible debug software such as MCUez, the SDI allows users to view and modify applications on the fly - reducing development time and speeding time to market.

    MCUez DEVELOPMENT TOOLSET
    MCUez is a user-friendly development environment used to develop applications in assembly language and to debug assembly and C applications based on Motorola's 8- and 16-bit microcontrollers. The MCUez toolset is designed to leverage the speed and efficient memory utilization provided by assembly language with a smart linker. Plus, the development environment's user-friendly interface and feature set help maximize designer productivity while minimizing time-to-market. Bundled with Motorola development hardware, the MCUez development toolset includes a configuration shell, assembler, linker, and debugger.