The overview information for the 68HC16 family of microcontrollers is included on this CD for your convenience. For specific information, please see CD1 of this CDROM set.

68HC16 CPU and Peripherals Overview

Click on any block diagram to enlarge

68HC16 Central Processor Unit (CPU16)

  • Enhanced 16-bit implementation of the 68HC11 CPU
  • Digital Signal Processing (DSP) functions
  • Background Debug™ Mode
  • High-level language support
  • 1 Mbyte data space
  • 1 Mbyte program space
  • Two 16-bit general-purpose accumulators
  • Three 16-bit index registers
  • Dynamic 8- or 16-bit bus sizing
  • Fast interrupt response time
  • 16 MHz, 20 MHz, and 25 MHz versions
  • 5.0 V as well as 2.7 V to 3.6 V

    • Time Processor Unit (TPU)
    The TPU is a semi-autonomous coprocessor dedicated to performing complex, high-speed timing tasks without CPU intervention.

  • 16 channels, each associated with an I/O pin, a 16-bit capture register, a 16-bit compare register, and a 16-bit greater than or equal to comparator
  • Two free-running 16-bit counters with programmable prescalers
  • A task-switched microengine that interfaces to each of the channels and executes microcode programs to control those channels
  • A control store (micro-ROM) that contains programs the microengine executes
  • A dual-port RAM to store custom TPU microcode or augment on-board data memory
  • TPU Library of more than 20 different timing functions
  • Most of which are in two standard micro-ROM mask sets
  • Others can be loaded into TPURAM to meet specific application requirements

    • Time Processor Unit 2 (TPU2)
    The TPU2 expands the TPU's micro-ROM control store from 2 Kbytes to 4 Kbytes, adds new instructions to simplify microcode programs, adds a fault detect input for TPU shutdown in the event of system failure, and improves timer event resolution by a factor of 2.

    General-Purpose Timer (GPT)
    The GPT is a simple, yet flexible 11-channel timer, well-suited for systems requiring a moderate degree of timing control.

  • Nine-stage prescaler (independent prescaler taps for capture/compare unit, PWM unit, and pulse accumulator)
  • One 16-bit free-running counter for capture/compare unit
  • Three input capture pins
  • Four output compare pins
  • One input capture/output compare pin
  • Second 16-bit free-running counter for two-channel PWM
  • Programmable duty cycle and 16 period choices
  • 8-bit resolution
  • An 8-bit pulse accumulator/event counter input
  • Independent clock source input pin

    • Configurable Timer Module (CTM)
    The CTM takes modularity one step further. This timer increases flexibility by defining its function in terms of individual submodules, allowing each device to be configured to match an application's requirements.
  • Counter submodules
  • Clock prescaler
  • 16-bit free-running counter
  • 16-bit modulus counter
  • Action submodules
  • Programmed I/O
  • Dual channel, single action input capture/output compare
  • Single channel, double action input capture/output compare with PWM mode
  • High-speed PWM
  • Real-time clock with external oscillator input
  • I/O pin for each input capture/output compare
  • Output-only pin for each PWM channel
  • External clock input capability
  • Interrupt capability on all capture/compare/PWM channels and on counter overflow conditions
  • Two, three, or four timebases, with two timebase options per action submodule
  • Battery backed data RAM

    • Controller Area Network Interface Module (TouCAN ™)
    The TouCAN module implements the Controller Area Network (CAN) protocol, an asynchronous communications protocol used in automotive and industrial control systems. CAN's high-speed (1 Mbit/sec), short distance, priority-based protocol runs over a variety of mediums, supporting both standard and extended identifier message formats. Motorola's TouCAN module offers full implementation of the CAN protocol specification, version 2.0A/B, with both standard data and remote frames (up to 109 bits long) and extended data and remote frames (up to 127 bits long). It also allows for 0 to 8 bytes data length and a programmable bit rate up to 1 Mbit/sec.

  • 16 receive/transmit message buffers of 0 to 8 bytes data length
  • Three programmable mask registers: global, for message buffers 0 through 13; special, for message buffer 14; and special, for message buffer 15
  • Programmable loop-back for self-test operation
  • Global network time, synchronized by specific message
  • Low-power sleep mode with programmable wakeup on bus activity

    • Queued Serial Module (QSM)
    The Queued Serial Module (QSM) contains two serial ports.

  • A Serial Peripheral Interface (SPI) with enhanced queued RAM and full-duplex, synchronous three-line bus
  • A Serial Communications Interface (SCI) provides standard asynchronous NRZ format with speeds up to 524 Kbaud
  • Four serial chip selects for flexible SPI peripheral addressing
  • Unused serial interface lines can provide up to eight general-purpose I/O pins

    • Multi-Channel Communications Interface (MCCI)
    The MCCI contains three serial interfaces: a Serial Peripheral Interface (SPI) and two Serial Communication Interfaces (SCI).

  • Two independent SCI ports provide standard asynchronous NRZ format at baud rates up to 524 Kbaud
  • One standard SPI allows easy system expansion to peripherals via a full-duplex synchronous three-line bus
  • Master mode and slave mode operation
  • Unused serial interface lines can provide up to eight general-purpose I/O pins

    • Analog-to-Digital Converter (ADC)
    The ADC module has eight channels, eight result registers and eight automated conversion modes. It also provides:
  • Selectable 8-bit or 10-bit resolution
  • Programmable sample and hold times
  • Three result alignment modes
  • 8-bit conversion in 8 microseconds; 10-bit conversion in 9 microseconds

    • Queued Analog-to-Digital Converter (QADC)
    The QADC is a 10-bit converter with automation features that handle complex data acquisition tasks.

  • Two independent queues controlling 40 result registers with three result alignment formats
  • 16 analog input channels or up to 44 when multiplexed externally
  • Alternate voltage reference and programmable sample and hold times
  • The queues can be set to perform continuous conversions or they may be started by either software commands, the QADC module periodic interval timer, or by an external trigger

    • System Integration Module (SIM)
    The SIM provides an external bus interface and system failure protection mechanisms including:

  • 12 programmable chip selects with programmable wait states
  • External bus supporting dynamic bus sizing
  • Watchdog timer
  • Seven external IRQ pins alternatively configurable as discrete I/O
  • Bus and software watchdog monitors
  • Phase-Locked Loop (PLL) clock system
  • Periodic Interrupt Timer (PIT)

    • Single-Chip Integration Module (SCIM)
    With all of the same features as the SIM, except as noted, the SCIM supports operation in expanded and single-chip modes.

  • Three operational modes
  • Fully expanded (SIM functionality or single-chip emulation with nine chip selects)
  • 8-bit data bus with Port H as an I/O port
  • Single-chip mode; Ports A, B, E, F, G, and H as I/O ports; Port C as output only

    • Single-Chip Integration Module 2 (SCIM2)
    The SCIM2 has the same features as the SCIM but also includes:

  • Improved reset controller
  • More flexible clock source selection

    • FLASH Electrically Erasable Programmable Read-Only Memory (FLASH EEPROM)

  • Support for byte, word, and long word operations
  • Fast 2 clock access speed
  • Word programmable, bulk erasable, non-volatile, 16-bit wide memory
  • Requires an external 12 V programming/erasure voltage source
  • 2 Kbyte Block Erasable EEPROM (BEFLASH) modules that provide byte/word programming with a 12 V external input
  • Eight independently-erasable various-sized blocks

    • Static RAM Module (SRAM)
    The Static Random Access Memory (SRAM) is available in 1, 1.5, 2, 3.5 and 4 Kbyte blocks, and provides fast 2 clock access speeds.

    Additionally, SRAM modules can be maintained while the MCU is powered down with just 3 V on the standby voltage pin.

    SRAM Module for TPU Microcode Storage (TPURAM)
    The TPURAM facilitates the use of custom or substitute TPU functions. When the TPU enters emulation mode, this SRAM module becomes dedicated to the TPU and replaces the TPU control store ROM. Different TPU functions may be downloaded to the TPURAM for execution by the TPU.

    Read-Only Memory (ROM)
    Also supporting byte, word, and long word operations, the ROM is available in 4 Kbyte increments from 4 to 64 Kbytes and provides fast 2 clock access speed. The ROM's 16-bit wide memory contents are masked on a custom basis.



    68HC16 Product Overview

    68HC16 Z Family:
    Lower-cost devices optimized for expanded memory applications that require high-performance serial communications and basic analog functions.

    68HC16 Y Family:
    Highly integrated single-chip devices with FLASH or ROM, time processor unit, three serial interfaces (two SCI and one SPI), and analog-to-digital converter.

    68HC16 X and R Families:
    Lower-cost, lower pin count, single-chip devices with FLASH, serial, and analog capabilities.



    68HC16 Development Tools Overview

    Motorola and more than 65 independent development tool suppliers provide 68HC16 and 683XX development tool support with: emulators, logic analyzers, programmers, evaluation boards, simulators, C compilers, real-time operating systems, assemblers, and debuggers - all allowing you to develop, monitor, test, and debug your code to get your applications up and running fast. Motorola's development tools include:

    MEVB1632 Modular Evaluation Board (MEVB)
    The MEVB aids hardware and software evaluation by providing essential microcontroller timing and I/O port replacement circuitry. It supports devices from the 68HC16 and 68300 Families (68HC16S2, 68HC16Y1, 68HC16Z1, 68331, 68332A, 68332G, 68F333C, 68376). The MEVB's flexibility, ease-of-use, and features make it a fast and economical tool for prototyping your application. The MEVB's features include:

  • Jumper-selectable support for multiple memory devices (FLASH EEPROM, EPROM, and RAM) and sizes from 32 to 512 Kbytes
  • Seven software breakpoints
  • Logic analyzer connection for all MCU pins
  • On-board FLASH EEPROM programming support
  • On-board wire-wrap area
  • Integrated development environment for assembling, editing, evaluating, programming, and source-level debugging (IASM16/32, ICD16/32, PROG16/32)
  • On-board programming voltage circuitry eliminates the need for a separate programming voltage power supply
  • PC host interface connection through Background Debug Mode and serial I/O expansion via RS-232C

    • MMDS1632 Modular Development System
    The MMDS1632 provides high-speed, real-time hardware and software emulation for target systems based on Motorola's 68HC16 and 68300 Families (68HC16S2, 68HC16Y1, 68HC16Z1, 68331, 68332A, 68332G, 68F333C, 68376). It includes a Station Module (SM) which houses a control board, internal power supply, and easy-access active probe connections, as well as host software to support target system emulation and bus analysis, and complete documentation. Additionally, the MMDS1632 Modular Development System's features include:

  • Real-time, in-circuit emulation
  • Four hardware breakpoints
  • More than 1 Mbyte built-in emulation memory with 4 Kbytes of real-time read/write memory
  • 96 channels real-time bus analysis, 52 Kbytes deep
  • 16 logic chips for individual signal selection and analysis
  • Built-in self-test

    • SDI ™ Serial Debug Interface
    The SDI is a serial in-circuit debugging tool that utilizes the Background Debug Mode on 68HC16, 68300, and MPC500 microcontrollers to quickly update and verify application code. When used with compatible debug software such as SDbug16 or SDbug32, developers can view and modify their application in real time.

    MCUinit ™ Rapid Initialization Software
    The MCUinit development tool simplifies and accelerates initialization of 68HC16 and 68300 microcontrollers. It includes a graphical user interface, on-line context-sensitive help, automatic code generation and rule checking, and debugging support when used with the MMDS1632. MCUinit software currently supports the 68HC16Y1, 68HC916Y1, 68HC16Z1, 68HC16Z2, 68331, 68332, 68F333, 68334, and 68360 microcontroller derivatives. On-chip IMB peripheral modules supported include the QSM, MCCI, TPU, GPT, SIM, SCIM, ADC, and various types of memory, such as SRAM, ROM, and FLASH EEPROM. Clicking on a particular IMB peripheral button opens configuration panels for the module. Users enter settings for the module, such as the clock rate, address range, timer functions, and baud rate by clicking a button or filling in a text box. Once selections are made, the MCUinit tool generates the initialization code in C or in assembly language. The code is fully commented for maintenance purposes, and users may add their own comments.