The overview information for the M·CORE family of microcontrollers is included on this CD for your convenience. For specific information, please see CD3 of this CDROM set.

M·CORE CPU and Peripheral Overview

Click on any block diagram to enlarge

M·CORE Integer Processor

  • 32-bit load/store RISC architecture
  • Fixed 16-bit instruction length
  • 16-entry, 32-bit general-purpose register file
  • Efficient 4-stage execution pipeline, hidden from application software
  • Single-cycle instruction execution for many instructions
  • Two cycles for taken branches and memory access instructions
  • Support for byte, halfword, and word memory accesses
  • Fast interrupt support with 16-entry dedicated alternate register file
  • Vectored and autovectored interrupt support
  • On-chip emulation support
  • Full static design for minimal power consumption


  • External Interface Module (EIM)

  • Transfers information between the CPU and external memory or peripherals
  • 20 to 32 address lines depending on implementation
  • 16 data lines
  • Chip select and wait state generation
  • Bus watchdog timer


  • Timer/Reset Module

  • Crystal oscillator: generates the master clock signal for the time-of-day timer from a 32.768-kHz external crystal
  • Time-of-day timer: provides time-of-day information as well as an alarm clock function
  • Watchdog timer: resets the chip to recover from system failure
  • Reset unit: provides low-voltage detection input and backup power switching for SRAM and the time-of-day timer
  • Periodic interrupt timer


  • Universal Asynchronous Receiver/Transmitter Module (UART)

  • Two independent UART channels
  • Asynchronous operation
  • Baud rate generation
  • Infrared (IR) interface support


  • Pulse-Width Modulation Module (PWM)

  • Six independent PWM channels
  • Programmable period
  • Programmable duty cycle
  • Periodic interrupt capability
  • Pins can be configured as general-purpose I/O


  • Interval Mode Serial Peripheral Interface (ISPI)

  • Efficient communication with slower serial peripherals
  • Designed for master/slave SPI operation
  • Interval mode SPI operation


  • M·CORE Product Overview

    MMC2001
    The first MCU to feature the flexible new M·CORE architecture from Motorola is a fast, ultra-low power controller chip that will bring highly cost effective performance to battery-powered systems.

  • 31 MIPS with an internal clock speed of 33 MHz with a 1.8 V supply (Dual supply voltage with I/O at 3.3 V)
  • 32 Kbytes of SRAM, with battery backup supply support
  • 256 Kbytes of mask-programmable ROM
  • Supplied with M-Bug Soft Debug module and I/O software driver code, or can be programmed with customer-specified code
  • Flexible interrupt controller with support for up to 32 interrupt sources
  • External interface module, supporting 20 address/16 data lines, chip select, wait-state generation, and a bus watchdog timer
  • Full-function timer/reset module
  • Serial communications via two independent asynchronous UARTs, with support for serial infrared communications
  • Interval serial peripheral interface (ISPI)
  • 16-bit general-purpose I/O port, with support for keyboard scan/encode
  • 8-bit general-purpose I/O port, with support for edge/level sensitive interrupts
  • Six independent pulse-width modulation (PWM) channels that can be alternately configured as general-purpose I/O
  • On-chip emulation (OnCE) debug module mapped onto the JTAG test access port, which supports background debug and emulation

  • Watch for announcements on new M·CORE products!



    M·CORE Development Tools Overview

    A solid selection of M·CORE dendors. Tools include highly optimized compilers, instruction-set simulators, debuggers, target monitors, software/hardware co-verification tools, real-time operating systems, and evaluation boards, as shown in the table below.




    To assure high-quality development tools, the M·CORE technology center developed an application binary interface standard that defines requirements for creating M·CORE toolchain components. Adherence to the standard guarantees interoperability with other ABI compliant tools and allows developers to evaluate and select tools based on performance, rather than compatibility. To provide additional support and protection, M·CORE development tools are fully tested to ensure "customer-ready" validation before release.

     
    CORE Development Tools
    Compilers/Debuggers
    Cosmic www.std.com/cosmic
    Diab Data www.ddi.com
    Green Hills www.ghs.com
    HIWARE www.hiware.com
    Metrowerks www.metrowerks.com
    Motorola GNU www.motorola.com/mcore
    Software Development Systems (SDS) www.sdsi.com


    Real-Time Operating Systems
    Accelerated Technology, Inc. www.atinucleus.com
    Embedded System Products www.esphou.com
    Integrated Systems www.isi.com
    Microware www.microware.com
    Microtec www.mentorg.com
    Precise Software Technologies www.psti.com
    Wind River Systems www.wrs.com


    Instruction Set Simulators
    Green Hills www.ghs.com
    HIWARE www.hiware.com
    Integrated Systems www.isi.com
    Software Development Systems (SDS) www.sdsi.com


    Software/Hardware Verification
    HIWARE www.hiware.com
    Mentor Graphics www.mentorg.com
    Summit www.summit-design.com
    ViewLogic/Eagle Design www.viewlogic.com


    Logic Analyzers
    Hewlett-Packard (Processor Probe, Logic Analyzer) www.hp.com
    iSystem Emulator www.isystem.com
    Tektronix (Logic Analyzer) www.tek.com


    Development Boards
    MMCEVB1200 www.motorola.com/mcore
    MMCCMB1200 www.motorola.com/mcore
    MMCFPGA1200 www.motorola.com/mcore
    MMCLAB01 www.motorola.com/mcore