Motorola 68HC08/12 CD-Rom

The overview information for the MPC5xx family of microcontrollers is included on this CD for your convenience. For specific information, please see CD3 of this CDROM set.

MPC5xx CPU and Peripheral Overview

Click on any block diagram to enlarge

RISC MCU Central Processor Unit (RCPU)

32-bit PowerPC Architecture (compliant with PowerPC Architecture Book 1)

Core performance measured at 52.7 K MIPS (Dhrystone 2.1) @ 40 MHz

Fully static, low-power operation

Integrated double precision floating-point unit

Precise exception model

Extensive system development support

On-chip watchpoints and breakpoints

Program flow tracking

On-chip emulation (OnCE™) development interface

Four-Bank Memory Controller

Works with SRAM, EPROM, FLASH EEPROM, and other peripherals

Byte write enables

32-bit address decodes with bit masks

Memory transfer start (MTS): This pin is the transfer start signal to access a slave's external memory by an external bus master

System Interface Unit (SIU) U-Bus System Interface Unit (USIU)

Clock synthesizer

Power management

Reset controller

PowerPC decrementer and timebase

Glueless interface to SRAMs and burstable FLASH

Real-time clock register

Periodic interrupt timer

Hardware bus monitor and software watchdog timer

Interrupt controller that supports up to eight external and eight internal interrupts

IEEE 1149.1 JTAG test access port

External bus interface

24 address pins, 32 data pins

Supports multiple master designs

Four-beat transfer bursts, two-clock minimum bus transactions

Tolerates 5-V inputs, provides 3.3-V outputs

Flexible Memory Protection Unit

Four instruction regions and four data regions

4-Kbyte to 16-Mbyte region size support

Default attributes available in one global entry

Attribute support for speculative accesses

General-Purpose I/O Support

Address (24) and data (32) pins can be used for general-purpose I/O in single-chip mode

Nine general-purpose I/O pins in MIOS1 unit

Many peripheral pins can be used for general-purpose I/O when not used for primary function

5-V outputs

Time Processor Unit (TPU3)

A dedicated micro-engine that operates independently of the RCPU

16 independent programmable channels and pins

Each channel has an event register consisting of a 16-bit capture register, a 16-bit compare register, and a 16-bit comparator

Nine pre-programmed timer functions are available

Any channel can perform any time function

Each timer function can be assigned to more than one channel

Two timer count registers with programmable prescalers

Each channel can be synchronized to one or both counters

Selectable channel priority levels

5-V outputs

18-Channel Modular I/O System (MIOS1)

Ten double action submodules (DASMs)

Eight dedicated PWM submodules (PWMSMs)

Two 16-bit modulus counter submodules (MCSMs)

Two parallel port I/O submodules (PIOSM)

5-V outputs

Queued Analog-to-Digital Converter Module (QADC)

Up to 16 analog input channels, using internal multiplexing

Up to 41 total input channels, using internal and external multiplexing

10-bit resolution with internal sample/hold

Typical conversion time of 10 msec (100,000 samples per second)

Two conversion command queues of variable length

Automated queue modes initiated by:

External edge trigger/level gate

Software command

64 result registers

Output data that is right- or left-justified, signed or unsigned

Controller Area Network Module (CAN)

Full implementation of CAN protocol specification, version 2.0 A and B

Each module has 16 receive/transmit message buffers of 0 to 8 bytes data length

Global mask register for message buffers 0 to 13

Independent mask registers for message buffers 14 and 15

Programmable transmit-first scheme: lowest ID or lowest buffer number

16-bit free-running timer for message time-stamping

Low-power sleep mode with programmable wakeup on bus activity

Programmable I/O modes

Maskable interrupts

Independent of the transmission medium (external transceiver is assumed)

Open network architecture

Multimaster concept

High immunity to EMI

Short latency time for high-priority messages

Queued Serial Multi-Channel Module (QSMCM)

Queued serial peripheral interface (QSPI)

Provides full-duplex communication port for peripheral expansion or interprocessor communication

Up to 32 preprogrammed transfers, reducing overhead

Has 160-byte queue

Programmable transfer length: from eight to 16 bits, inclusive

Synchronous interface with baud rate of up to system clock / 4

Four programmable peripheral-select pins support up to 16 devices

Wrap-around mode allows continuous sampling of a serial peripheral for efficient interfacing to serial A/D converters

Two serial communications interfaces (SCI), each offering these features:

UART mode provides NRZ format and half- or full-duplex interface

16 register receive buffer and 16 register transmit buffer (SCI1)

Advanced error detection and optional parity generation and detection

Word length programmable as eight or nine bits

Separate transmitter and receiver enable bits and double buffering of data

Wakeup functions allow the CPU to run uninterrupted until either a true idle line is detected or a new address byte is received

External source clock for baud generation

Multiplexing of transmit data pins with discrete outputs and receive data pins with discrete inputs

MPC555 Product Overview

PowerPC core with floating-point unit

26 Kbytes fast SRAM and 6 Kbytes TPU microcode SRAM

448 Kbytes FLASH EEPROM with 5-V programming

5-V I/O system

Serial system: queued serial multi-channel module (QSMCM)

Dual CAN 2.0B controller modules (TouCAN)

50-channel timer system with dual time processor units (TPU3) and modular I/O system (MIOS1)

32 analog inputs: Dual queued analog-to-digital converters (QADC64)

272-pin plastic ball grid array (PBGA) packaging

40-MHz operation, -40° C to 125° C with dual supply (3.3 V, 5 V)

MPC5XX Development Tool Overview

A solid selection of MPC5XX development tools are available from Motorola, Inc. and from established third-party vendors. Tools include highly optimized compilers, debuggers, target monitors, software/hardware co-verification tools, real-time operating systems, and evaluation boards. To assure high-quality development tools, an application binary interface standard was developed that defines requirements for creating MPC5XX toolchain components. Adherence to the standard guarantees interoperability with other ABI compliant tools and allows developers to evaluate and select tools based on performance, rather than compatibility.