Message Data Link Controller

SAE J1850 Protocol

The Message Data Link Controller (MDLC) incorporates a serial communication multiplex bus that operates according to the SAE J1850 Protocol. Multiple microcontrollers with the MDLC module can communicate over a single or dual wire bus, eliminating the weight and bulk of wire harnesses and adding diagnostic capability.


SOME PROPERTIES OF THE MDLC MODULE:

  • Single Transmit Buffer

  • Dual Ping Pong Receive Buffers

  • Integrated J1850 VPW Physical Interface

  • Supports Messages of Unlimited Length

  • Optional CPU Interrupt Capability

  • Automatic Transmission Retry Following Loss Of Arbitration

  • Supports 10.4KBPS J1850-VPW Communication Only

  • Very Low CPU Overhead, Typically 5%

  • Power Saving Module Stop and Wait Modes With Optional WakeUp on Network Activity



SAE Standard J1850 Class B Data Communication Network Interface (J1850)

The J1850 protocol encompasses the lowest two layers of the International Standards Organization (ISO) open system interconnect (OSI) model, the data link layer and the physical layer. It is a multi-master system, utilizing the concept of carrier sense multiple access with collision resolution (CSMA/CR), whereby any node can transmit if it has determined the bus to be free. Non-destructive arbitration is performed on a bit-by-bit basis whenever multiple nodes begin to transmit simultaneously. J1850 allows for the use of a single or dual wire bus, two data rates (10.4 kbps or 41.7 kbps), and two bit encoding techniques (pulse width modulation (PWM) or variable pulse width modulation (VPW)).

A J1850 message, or frame, consists of a start of frame (SOF) delimiter, a one- or three-byte header, zero to eight data bytes, a cyclical redundancy check (CRC) byte, an end of data (EOD) delimiter, and an optional in-frame response, followed by an end of frame (EOF) delimiter. Frames using a single byte header are transmitted at 10.4 kbps, using VPW modulation, and contain a CRC byte for error detection. Frames using a one-byte consolidated header or a three-byte consolidated header can be transmitted at either 41.7 kbps or 10.4 kbps, using either PWM or VPW modulation techniques, and also contain a CRC byte for error detection.

Each frame can contain up to 12 bytes (VPW) or 101 bit times (PWM), with each byte transmitted MSB first. The optional in-frame response can contain either a single byte or multiple bytes, with or without a CRC byte. The requirements of each individual network determine which features are used.