TI extends the ’C6000 platform to new levels of performance and affordability

The recently disclosed digital signal processors (DSPs) from Texas Instruments will expand the world of embedded DSP applications by pushing the performance envelope and shattering price barriers.

The TMS320C6202 and TMS320C6211, additions to the world’s most powerful DSP platform, will help designers accelerate development of products for wireless video teleconferencing, wireless e-mail, superfast Internet access and more.

Both devices use the same advanced Very Long Instruction Word (VLIW) VelociTI™ architecture that TI developed for its industry-leading ’C6201 fixed-point DSP, in volume production now. Instruction-set software compatibility with the ’C6201 allows developers to begin coding and debugging ’C6202 or ’C6211 designs today.

The ’C6202 offers twice the MIPS per square centimeter over the ’C6201, a 25 percent increase in performance at 2000 MIPS and a 40 percent reduction in package size. In addition, the ’C6202 triples on-chip memory and doubles chip I/O bandwidth for faster data throughput and greater system performance.

The 250-MHz ’C6202 integrates three megabits of on-chip RAM, tripling the memory of the ’C6201. Like the ’C6211, the ’C6202 integrates two 32-bit timers and two multi-channel buffered serial ports (McBSPs).

The device features a new 32-bit asynchronous expansion bus that complements the primary, synchronous external memory interface (EMIF) bus, providing an almost glueless interface to PCI bridges. The expansion bus offers a glueless FIFO interface, which helps free up the EMIF for real-time, synchronous operation.

The ’C6211 features 1200 MIPS of fixed-point performance at US $25 each in 25K quantities, and delivers nearly two cents per MIPS for cost-sensitive small office and home office (SOHOs) applications like digital subscriber loop (DSL) client units, high-speed data transmission functions in switches and routers, wireless data clients, imaging, biometrics, remote medical diagnostics, automotive vehicle and drive train control, and security systems.

The ’C6211 uses an innovative 2-level cache memory configuration that enables faster access with a relatively inexpensive integrated memory. Benchmarks show that the ’C6201 achieves more than 80 percent of ’C6201 performance running with all memory on-chip.

Integrated peripherals include a 32-bit EMIF with synchronous access to 1 gigabyte of off-chip memory, enhanced direct memory access (DMA), two 32-bit timers and two McBSPs for T1/E1 interface.

Typical internal power consumption of the ’C6211 is 1.5 watts and 1.9 watts for the ’C6202. All ’C62x products will be offered in new 27-millimeter ball grid arrays (BGAs).

www.ti.com/sc/c62x

TMS320C62x Digital Signal Processor
Device	Internal Cycle Time	Nominal Voltage	On-Chip Memory	Synchronous Memory Interface	Host Port Interface (HPI)/Expansion Bus	McBSP¹	Direct Memory Access (DMA)	Package	Scheduled Availability
									Samples	Volume
TMS320C6201-167	6 ns	2.5/3.3V	128 Kbytes RAM	32-bit	HPI/16-bit	2	4	352-pin BGA 35 mm

TMS320C6201-200	5 ns	2.5/3.3V	128 Kbytes RAM	32-bit	HPI/16-bit	2	4	352-pin BGA 35 mm

TMS320C6201B-200	5 ns	1.8/3.3V	128 Kbytes RAM	32-bit	HPI/16-bit	2	4	352-pin BGA 35 mm/27 mm		1Q99

TMS320C6202-250	4 ns	1.8/3.3V	384 Kbytes RAM	32-bit	Exp. Bus/32-bit	2	4	352-pin BGA 27 mm	1Q99	3Q99

TMS320C6211-150	6.7 ns	1.8/3.3V	72 Kbytes cache²	32-bit	HPI/16-bit	2	16 (Enhanced DMA)	256-pin BGA 27 mm	2Q99	2H99

¹ McBSP= Multi-channel Buffered Serial Port ² The ’C6211’s 72 Kbytes of cache memory is comprised of 4 Kbytes data cache (L1D), 4 Kbytes program cache (L1P), and 64 Kbytes unified cache/memory (L2).