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TMS320C54x DSP programming
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TMS320C54x DSP programming environment: The TMS320C54x DSP family began as the Low-Power Enhanced Architecture DSP (LEAD) project. The project goal was a fixed-point DSP with power-saving characteristics well-suited for the cellular telephone market. The result is a multi-bus design with special CPU features such as two accumulators and dual addressing modes that support many diverse application areas in addition to cellular telephones. The TMS320C54x architecture is a departure from the 'C2x/'C5x family, but shares many peripherals and interface features with its cousins. The TMS320C54x User's Guide gives a detailed description of the architecture. This application brief discusses elements of the programming style used with this processor.

Basic Architecture

Many DSPs are based around a Harvard architecture with separate data and program memories and associated buses. The TMS320C54x devices share this feature, but additional data buses embellish the architecture and improve throughput.

The TMS320C54x family of devices shares the following features:

• 50 MIPS performance
  
• 3.0, 3.3 and 5-V versions available
  
• Integrated Viterbi operation
  
• Three power-down modes
  
• Integrated ROM and RAM configurations
  
• Several serial port options
  
• Host port interface
  
• Ultra-thin packaging
  

The complete application report can be found at: http://www.ti.com/sc/docs/psheets/appnote.htm. The TMS320C54x User's Guide can be found at: http://www.ti.com/sc/docs/psheets/manuals.htm.