New RMII spec for easier switching
RMII for Ethernet PHYs equals lower-cost, higher-density networking devices
A new specification for a Reduced Media Independent Interface (RMII) will make network switching solutions easier and cheaper for system providers to build.
Jointly developed by Texas Instruments, Advanced Micro Devices, Broadcom Corp. and National Semiconductor Corp., the RMII specification is intended for use between 10/100Mbps Ethernet physical layer interface (PHY) devices and switch silicon. It reduces the complexity of the interface between the media access controller (MAC) and PHY components.
The Ethernet standard (IEEE 802.3µ) defines an MII with 16 pins per port for data and control. In devices incorporating many MAC or PHY interfaces such as switches or port-switched repeaters, the number of pins can add significant costs as port counts increase. For example, in a typical 24-port switch configuration, the RMII could reduce the number of MAC pins from 16 to six per port, for a savings of 239 pins. (One pin has been reserved for clock function.)
The RMII reduces PHY costs while maintaining features currently available in PHY layer silicon:
- All the functionality of 802.3µ MII.
- Operation at either 10 Mbps or 100 Mbps data rates, supporting the migration toward high-speed Ethernet products.
- Implementation of a single synchronous clock reference sourced from the MAC to PHY (or from an external source) to simplify the clocking interface.
- Support for existing features such as full-duplex capability in switches.
The RMII is optimized for use in high-port-density interconnect devices, primarily network switch ASICs requiring independent treatment of the data paths between the MAC and PHY. The RMII is also useful for port-switched repeater ASICs that integrate more than one repeater core and provide a mapping function between PHY interfaces and internal segments.
Key RMII features
- Offers more that 60 percent reduction of pins over 802.3u MII (from 16 pins to six)
- Supports 10 Mb/s and 100Mb/s data rates
- Provides single synchronous clock reference
- Creates independnet 2-bit wide transmit and receive data paths
- Offers pin count independent of port density
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