The MC9S12DP256 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (STAR12 CPU), 256K bytes of Flash EEPROM, 12.0K bytes of RAM, 4.0K bytes of EEPROM, 2 asynchronous serial communications interfaces (SCI), three serial peripheral interfaces (SPI), an 8 channel IC/OC enhanced capture timer, two 8-channel, 10-bit analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), a digital Byte Data Link Controller (BDLC), 89 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital I/O lines with interrupt and wakeup capability, five CAN 2.0 A, B software compatible modules (MSCAN12), and an Inter-IC Bus. System resource mapping, clock generation, interrupt control and bus interfacing are managed by the System Integration Module (SIM). The MC9S12DP256 has full 16-bit data paths throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements.

• 16-bit STAR12 CPU
• Upward compatible with M68HC11 instruction set
• Interrupt stacking and programmer's model identical to M68HC11
• 20-bit ALU
• Instruction pipe
• Enhanced indexed addressing
• Multiplexed External Bus
• Memory
• 256K byte Flash EEPROM
• 4.0K byte EEPROM
• 12.0K byte RAM
Two 8 channel Analog-to-Digital Converters
• 10-bit resolution
• Five 1M bit per second, CAN 2.0 A, B software compatible modules
• Four receive and three transmit buffers
• Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
• Four separate interrupt channels for Rx, Tx, error and wake-up
• Low-pass filter wake-up function
• Loop-back for self test operation
• Time-stamping capabilities for network synchronization
• 8 channel IC/OC Enhanced Capture Timer
• Byte Data Link Controller (BDLC)
• Inter-IC Bus (IIC)
• 8 PWM channels with programmable period and duty cycle
• Standard 8-bit 8-channel or 16-bit 4-channel or any combination of 8/16 bit
• Separate control for each pulse width and duty cycle
• Left-aligned or center-aligned outputs
• Programmable clock select logic with a wide range of frequencies
• Fast emergency shutdown input
• Usable as interrupt inputs
• Serial interfaces
• Two asynchronous Serial Communications Interfaces (SCI)
• Three synchronous Serial Peripheral Interfaces (SPI)
• SIM (System integration module)
• CRG (low current oscillator, PLL, reset, clocks, COP watchdog, real time interrupt, clock monitor)
• MEBI (Multiplexed External Bus Interface)
• MMC (Module Mapping Control)
• INT (Interrupt control)
• BKP (Breakpoints)
• BDM (Background Debug Mode)
• 112-Pin LQFP package
• 50 MHz CPU equivalent to 25MHz bus operation
• 2.25 to 2.75V Digital Supply Voltage generated using an internal voltage regulator
• 4.75V to 5.25V Analog and I/O Supply Voltage
• Technology: 0.25 micron CMOS

   

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