The MC68HC912D60 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (CPU12), 60-Kbyte flash EEPROM, 2-Kbyte RAM, 1-Kbyte EEPROM, a dual asynchronous serial communications interface (SCI), a serial peripheral interface (SPI), an 8-channel enhanced capture timer and 16-bit pulse accumulator, a 10-bit analog-to-digital converter (ADC) with up to 16 channels, a four-channel pulse-width modulator (PWM), and a CAN 2.0B compatible controller (MSCAN12). System resource mapping, clock generation, interrupt control and bus interfacing are managed by the Lite integration module (LIM). The MC68HC912D60 has full 16-bit data paths throughout, however, the multiplexed external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems.

• 16-Bit CPU12
  • Upward Compatible with M68HC11 Instruction Set
  • Interrupt Stacking and Programmer's Model Identical to M68HC11
  • 20-Bit ALU
  • Instruction Queue
  • Enhanced Indexed Addressing
  • Fuzzy Logic Instructions
• Multiplexed Bus
  • Single Chip or Expanded
  • 16/16 Wide or 16/8 Narrow Modes
• Memory
  • 60-Kbyte Flash EEPROM with 2-Kbyte Erase-Protected Boot Block
  • 1-KByte EEPROM
  • 2-Kbyte RAM with Single-Cycle Access for Aligned or Misaligned Read/Write
• Up to 16 Channel, 10-Bit Analog-to-Digital Converter
• 8-Channel Enhanced Capture Timer
  • Each Channel Fully Configurable as Either Input Capture or Output Compare
  • Simple PWM Mode
  • Modulo Reset of Timer Counter
• 16-Bit Pulse Accumulator
  • External Event Counting
  • Gated Time Accumulation
• Pulse-Width Modulator
  • 8-Bit, 4-Channel or 16-Bit, 2-Channel
  • Separate Control for Each Pulse Width and Duty Cycle
  • Programmable Center-Aligned or Left-Aligned Outputs
• Serial Interfaces
  • Dual Asynchronous Serial Communications Interface (SCI)
  • Synchronous Serial Peripheral Interface (SPI)
• Motorola Scalable CAN Controller (MSCAN12)
  • CAN 2.0B compatible (standard and extended identifiers)
  • Two receive and three transmit buffers
  • Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit
  • Four separate interrupt channels for Rx, Tx, error and wake-up
  • Low-pass filter wake-up function
  • Loop-back mode for self test operation
• COP Watchdog Timer, Clock Monitor, and Periodic Interrupt Timer
• 80-Pin QFP Package
• 112-Pin LQFP Package
  • Up to 63 General-Purpose I/O Lines
  • 4.5V - 5.5V Operation at 8 MHz
• Single-Wire Background Debug(tm) Mode (BDM)
• On-Chip Hardware Breakpoints