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PLL clock drivers

TI's new family of high performance phase-lock-loop (PLL) Clock Distribution Circuits (CDCs) features the CDC509, CDC516, CDC2509, CDC2509A, CDC2510, CDC2510A and CDC2516. The target applications for these devices are SDRAM dual-inline memory modules (DIMMs) for PCs, servers and workstations, however, they can also be used for general purpose clocking.

These CDCs support PC bus speeds of up to 100 MHz, which is part of Intel's PC100 specification, the new high-speed standard for synchronous memory interface on computer motherboards.

Each device is designed to align precisely, both in frequency and in phase, the feedback output (FBOUT) to the clock (CLK) input signal. Compared to other PLL devices, the family features integrated loop filter, alleviating the need for external components and reducing board space and cost. External feedback input (FBIN) enable each device to be used as a zero delay buffer. With their low voltage (3.3 V) and low power capabilities, these devices are optimized to reduce switching noise. Integrated series damping resistors make the 2000-series suitable for driving point-to-point loads. Devices in the 500-series are designed to drive multiple memory loads.

CDC2509A and CDC2510A also support Spread Spectrum modulation of timing signals, a technique that reduces the system electromagnetic interference or EMI.

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