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TI and Synopsys join forces to provide advanced ASIC design methodologies

Texas Instruments and Synopsys Inc. have announced a joint development effort to provide system-level, application-specific integrated circuit (ASIC) design capability for the creation of advanced System Level Integration (SLI), or "system-on-a-chip," components based on 0.25-micron technology and 0.18-micron TImeline Technology.

Ongoing development will provide TI internal developers and customers with new, flexible, easy-to-use design reuse methodologies for major improvements in design capability. These design methodologies will be available beginning in the fourth quarter of this year.

TI and Synopsys' Professional Services have worked for the past year to develop an SLI design environment integrating best-in-class features from a variety of sources into TI's ASIC design flows. The effort included hardware description language (HDL) coding guidelines, a customized version of Synopsys Design Environment (SDE) and silicon implementation methodologies ranging from the conceptual level down to the layout of individual gates. The resulting new environment brings greater consistency, robustness, simplicity, flexibility and design reuse to both standard cell and gate array designs.

The consistency of the new flows will enhance TI's ability to share information among design groups. It also will enable the company to pass the same information more effectively to its ASIC customers. At the same time, the flows' simplicity will reduce time-to-market. Synopsys, a leading supplier of electronic design solutions, will support and maintain the flows, giving TI and its customers a valuable source of design and methodology expertise.

Synopsys is a registered trademark.

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