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Meeting the DSP challenge
DSP designs of the future
'Tool Up' program allows
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DSP Solutions: Analog and
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   Memory
64M DSRAM at PC100 spec
TI devlops new process to
   assemble DRAM chips

   Mixed-Signal and Analog
App Report: Understanding
   operational amplifier
   specifications
1394 native bridge link
   controller IC
PLL clock drivers
Long-duration speech processor
Hot plug controller
2.5-V SOT-23 supervisor with
   watchdog timer

   Business News
TI DSP chip wins innovation
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TI and Synopsys join forces to
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Long-duration speech processor

With a 4K internal ROM, 1024 RAM locations and 28 software-
configurable I/O pins, the MSP50C30 long-duration speech processor features the same 8-bit microprocessor and dual synthesis channels found in TI's other MSP50C3x devices. This new device contains 23 address and eight data lines that allow a direct interface to external ROM (up to 8 Mbytes). With the external memory interface, the MSP50C30 is capable of long-duration speech synthesis of up to eight hours of Linear Predictive Coding (LPC).

The 28 I/O pins are configurable under software control to be either inputs or outputs. A number of low bit-rate speech synthesis algorithms such as LPC, Mixed Excitation Linear Prediction (MELP) and Code Excited Linear Prediction (CELP) are available for use with the MSP50C30. These options provide great flexibility in data space use and speech quality. FM Synthesis and ADPCM are other options available for use with this device, which is suitable for learning aids, talking books, games and toys, navigation systems, fitness equipment, warning systems and voice mailboxes.

Mask options also are available on the MSP50C30. These include DAC output options (two-pin digital or one-pin analog), a choice of an internal or external clock and package type (die or 100-pin QFP). Development tools supporting the MSP50C30 include an emulator and an assembler, which are used in the code development process. These tools allow users to compile, set breakpoints, single step through code and examine/modify registers and memory in order to debug their code.

MSP50C30 features
  • External ROM interface (up to 8 Mbytes)

  • Low bit rate synthesis algorithms (LPC, MELP, CLEP)

  • Internal clock generator

  • Code execution from external memory

  • Characterized for oepration 0°C to 70°C

For complete information, order: Product Literature. See Related Product Information

MSP50C30 diagram

MSP50C3X family of synthesizers

  MSP50C30 MSP50C32 MSP50C33 MSP50C34 MSP50P34 MSP50C37 MSP50P37

ROM Type
ROM
ROM
ROM
ROM
OTP
ROM
OTP
ROM (bytes)
4K
16K
32K
64K
64K
16K
6K

No. of RAM locations
1024
256
256
256
256
256
256
I/O Pins (packaged)
28
10
10
10
10
18
18

I/O Pins (die)
28
10
10
24
24
18
18
A/D Input
No
No
No
No
No
Yes
Yes

Linear Amp
No
No
No
No
No
Yes
Yes
Pin Count (packaged)
100
16
16
16
16
28
28

Pin Count (die)
68
16
16
40
40
28
28

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